The present invention relates generally to computer processor systems, and more specifically, lightweight interrupts for floating point exceptions in a computer processor system.
In computer systems that require a variety of system functions to be controlled in a nonsequential fashion, it is a common practice to employ interrupts to determine the order in which various operations are to be performed by the processor. An interrupt is generated in response to the occurrence of a predetermined event in the operation of the system. When the processor receives an interrupt request, it stops its present operation at an appropriate point and proceeds to a predetermined subroutine that controls the function associated with that particular interrupt. The predetermined condition may be an exception condition in the processor. The occurrence of an exception may result in generation of an interrupt that passes control from an application that was running at the time the exception occurred to supervisor software, so that the supervisor software can handle the exception. However, processing of interrupts by the supervisor software may negatively impact performance of the computer system.